Dr. Khalid Abed, a faculty member in the Department of Computer Engineering at JSU, is the principal investigator on this research effort, which deals with accelerating scientific applications with high performance reconfigurable computing (HPRC). "Microprocessor-based HPC clusters are facing formidable challenges such as run time performance, memory bottlenecks, floor space, and power dissipation. HPRC is emerging as a new research area that may provide solutions to some of these challenges. The SRC-7 system will allow us to investigate how to map complex parallel codes onto HPRC clusters", Professor Abed further noted. "Reconfigurable supercomputers allow researchers to reconfigure the hardware for different computing applications to achieve optimum performance for such applications instead of running different types of applications on a fixed supercomputer."

Dr. Gerald Morris, a computer scientist at the ERDC Department of Defense (DoD) Supercomputing Resource Center (DSRC), who is the Government technical lead on the project, believes that SRC advances in reconfigurable computing may have a considerable impact on the programme. "A significant benefit of this system is the SRC Carte Programming Environment. Carte allows the development of hardware-based computational kernels using either high-level languages like C or Fortran or hardware description languages like VHDL or Verilog." Dr. Morris added: "Carte abstracts away some of the underlying design details. This is particularly important when trying to map floating-point applications onto reconfigurable hardware, which is still a challenging research area."

Jon Huppenthal, President and CEO of SRC Computers, stated: "This system is built using the same commercial off-the-shelf (COTS) modules that we have qualified for airborne use, making it an ideal choice for military applications. We're very proud that our systems are being used to advance our country's military capabilities."