We have witnessed a long history of continuous increase of supercomputer performances to arrive now at the new petaflop machine, Dr. Robin explained to the audience. From 1975 to now, there has been an enormous evolution in the supercomputer TOP500 starting from scalar to vector machines, over vector and MPP machines, to clusters of SMP, and finally clusters of SMP with accelerators.

Complementary and interconnected centres are the building blocks of the PRACE infrastructure consisting of Tier-2 DEISA, Tier-1 and Tier-0 centres. Findings from PRACE meetings with top 50 system manufacturers in February 2008 have shown that several factors have an important impact on computer architectures. In this regard, different architectures will become scalable to petaflop's in 2009/2010, according to Dr. Robin. Whether MPP or cluster of SMP, none of them is likely to be optimal for all applications.

The evolution of technology will be constraint by acceptable power consumption and will lead to the need of a very high level of parallelism to reach 1 Petflop/s. The memory hierarchy gets more complex with widening gaps. This has a crucial impact both on supercomputer, design and operation, and on the tools and applications, the speaker pointed out.

Compute nodes, IO and service constitute the ingredients for a Petaflop/s system in 2009/2010. As for the evolution in the processors, the CPU will be evolving towards multi-core processors, motivated by energy-efficient performance and by the limitation of ILP. The trend indicates an increase of 2x the number of cores every 18 months.

From the accelerator side, we see an outstanding performance/cycle and a performance/electricity ratio for well suited and programmed applications, as Dr. Robin stated. There will be an integration of accelerators into compute nodes. The goal is to reduce overhead by speeding and uplimiting the data transfers.

Processors and accelerators will become hybrid and multi-core with a mixture of large and small cores, and of cores and accelerators. The option for many-core architectures means a large number of small cores on a chip with possibly specific hardware.

Other trends involve an increased need for optical interconnect and an increasing importance of data and IOs with a development towards the data-centric computing centre, distributed and parallel file systems, data integrity, and a heterogeneous configuration with nodes and an interconnection network, according to the speaker.

Dr. Robin described the typical configuration of a sustained Petaflop/s system in 2009/2010 as follows:

• 10 Gflops/core
• 6-8 cores/socket
• 2-4 sockets/node
• 100.000 cores
• 1000's of nodes
• possibly accelerators
• possibly heterogeneous

Major challenges are to be found in the performance of computation and IO, in the total cost of ownership, the programmability, scalability, and reliability. Some ways to address these challenges will be accelerators because they are potentially faster than processors, and parallel programming languages such as OpenMP and MPI. PGAS languages are gaining acceptance and performance with hardware support. In the longer term, Dr. Robin predicts the use of DARPA/HPCS, Chapel (Cray), X10 (IBM), and Fortress (Sun).

There will be a strong need for libraries and ISV applications because of the insisting trend towards parallelism.

The cost of electricity also constitutes an important factor. In order to achieve energy efficiency, IT equipments will make use of green power efficient components, processors, disks, power supplies, and fans. Power chain efficiency will avoid several voltage conversions and water cooling will be provided for by cooling doors or the direct cooling of electronic components, Dr. Robin predicted.

As for the reliability, what is important is the availability of the resources from the user point of view. It is a question of reaching a good availability ratio. Of course, there are always faulty components in a large supercomputer.

For PRACE understanding the major HPC trends is of critical importance for both taking advantage of future promising technologies and architectures, to play an active role in the European HPC ecosystem and its relationship with international high end initiatives, and for interacting with vendors and fostering their presence in Europe. Therefore Dr. Robin told the attendees that the main action for PRACE is to meet with the vendors.

The PRACE prototypes are essential tools for preparing the design and the deployment of the future HPC infrastructure. For the initial deployment of the PRACE infrastructure, the partners have to match current and future application requirements with vendor roadmaps and ensure an easy integration of the future supercomputers. At present, there are six prototypes selected that will be deployed in the next months.

Future leading edge supercomputers will provide a greatly increased performance and will be fantastic tools for research and industry, promised Dr. Robin. PRACE is working on the challenges that will be necessary to address in order to be able to influence and to make the best use of future architectures and technologies, he concluded.